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Mentor Graphics Advances Scalable Verification
New ModelSim Version Plus Assertion Technology from
Recently Acquired 0-In Design Automation Expands Functional
Verification Methodology
WILSONVILLE, Ore.—(BUSINESS WIRE)—Oct. 4, 2004—
Mentor Graphics (Nasdaq:MENT) today announced key extensions to
its Scalable Verification(TM) solution with a new version of its
popular ModelSim(R) simulator and advanced verification technology
from the recently completed acquisition of 0-In(R) Design Automation.
With the ModelSim 6.0 simulator and the 0-In product line, Mentor
Graphics(R) now offers standards-based support for the most advanced
verification methodologies. Offering support for assertion-based
verification and coverage-driven verification flows, as well as
verification IP, Mentor's Scalable Verification platform offers
engineers a faster way to reach verification closure than current
methods.
"Existing verification methodologies have run out of steam," said
Robert Hum, vice-president and general manager, Design Verification
and Test Division, Mentor Graphics. "Designers are looking for new
solutions that can dramatically increase their productivity.
Methodologies and tools like assertions, static analysis, functional
coverage, and coverage-driven verification are required to close the
verification gap. New capabilities in our ModelSim 6.0 release and the
acquisition of the 0-In products enable us to deliver these advanced
solutions today."
The ModelSim 6.0 Simulator: Core of Scalable Verification
Mentor's Scalable Verification solution is centered on the
ModelSim simulation environment, with industry leading standards
support for Verilog 2001, VHDL, PSL, SystemC and SystemVerilog. The
ModelSim 6.0 tool offers engineers verification methodology
enhancements to support better and faster verification including
support for assertion-based verification, functional coverage, and
coverage-driven verification.
Offering a native assertion engine as well as assertion debugging,
the ModelSim 6.0 product provides verification engineers a better way
of testing designs. Using assertion-based verification (ABV),
verification engineers can more easily test a design to ensure the
design matches its functional specification. The ModelSim 6.0
simulator also includes functional coverage capabilities that allow
engineers to track the effectiveness of their verification efforts.
Combining assertions with functional coverage enables coverage-driven
verification, in which designers use feedback from testing to target
their successive tests, resulting in greatly improved productivity and
effectiveness.
The new features in the ModelSim 6.0 simulator extend across
Mentor's Scalable Verification platform. Tighter integration with the
Seamless(R) Co-Verification Environment, Mentor's industry-leading
hardware/software co-verification tool, the VStation(TM) family of
emulators, and the ADVance(TM) MS high-performance analog/mixed-signal
simulator, provides designers with state-of-the-art verification of
the analog, digital and software verification problems they face
today.
Advancing Verification with 0-In Design Automation
The acquisition of 0-In Design Automation extends Mentor Graphics
verification solution with a world-class engineering team including
well-known experts in synthesis, formal analysis and assertion-based
verification. Twelve of the 15 largest electronics companies have
already adopted the 0-In tools and methodologies in their integrated
circuit (IC) design verification flows.
Combining static and dynamic techniques, the 0-In tools offer
unique technology that makes it possible to find more bugs quickly and
efficiently. The tools enhance the value of both simulation and
emulation verification technologies. For example, by enabling
assertion-based verification and functional coverage on the VStation
series of emulators, the tools enable designers to capture
completeness metrics on their high-performance emulation runs, greatly
enhancing their ability to calculate how complete their testing cycle
is.
"We chose the 0-In products, because of the attractiveness of
their existing product line and promise of the future," said Hum. "A
lot of products in this space aren't battle-tested, and we are
thrilled to have acquired mature products that are working in key
customers' flows today. With the reach of the Mentor sales force,
we'll be able to bring the 0-In solutions to a much wider selection of
customers."
Mentor Graphics will continue to support the 0-In existing
products and customers and will expand distribution and support of
these products with Mentor Graphics' global sales and support
organization. 0-In products will become part of the Mentor Graphics
Scalable Verification platform and also continue to work with products
from other EDA vendors.
About Mentor Graphics Scalable Verification Solution
The Mentor Graphics Scalable Verification solution is the most
comprehensive EDA approach to functional verification, merging
standards support, tools and a "design for verification" methodology
to minimize verification cycles and costly design respins. This
solution provides the industry's best language support and the most
complete path for verification, from HDL simulation to in-circuit
emulation, including support for testbenches, assertions and
functional prototypes. The Scalable Verification solution comprises
"best-in-class" technologies: the ModelSim simulation environment,
Seamless Hardware/Software Co-Verification, ADVance MS for
analog/mixed-signal verification, FormalPro(TM) equivalence checking
and the VStation and Celaro hardware emulation platforms. For more
details on Mentor Graphics Scalable Verification, go to
www.mentor.com/fv.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$675 million and employs approximately 3,800 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: http://www.mentor.com/.
Mentor Graphics, ModelSim, 0-In and Seamless are registered
trademarks and ADVance MS, FormalPro, VStation, Scalable Verification
and Celaro are trademarks of Mentor Graphics Corporation. All other
company or product names are the registered trademarks or trademarks
of their respective owners.
Contact:
Mentor Graphics
Larry Toda, 503-685-1664
larry_toda@mentor.com
or
Weber Shandwick
Hayley Luz, 503-552-3726
hluz@webershandwick.com
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